The invention relates to a nonvolatile semiconductor memory, and in particular, is concerned with a configuration of a mask ROM (Read Only Memory) wherein stored data is programmable by mask wiring.
With the mask ROM, data is fixedly stored by selectively forming metal interconnections in a storage with the use of a mask for a wiring pattern during a manufacturing process. The mask ROM includes a NAND type mask ROM, or a NOR type mask ROM, depending on a configuration of interconnection among memory cells. With the NAND type mask ROM, a plurality of memory cells are connected in series to each other between a bit line and a source line. Further, as is so often the case, data is stored by adjusting the threshold voltages of respective transistors of the memory cells through implantation of a dopant, thereby setting the respective transistors to an enhancement mode or a depletion mode.
With the NOR type mask ROM, one memory cell interconnects a bit line, and a source line. The one memory cell has a configuration wherein data is fixedly stored by selectively forming an interconnection between a transistor and the source line or the bit line by mask wiring, or a configuration wherein stored data is fixedly programmed by adjusting the threshold voltage of a memory cell transistor through implantation of a dopant, thereby setting the transistor to the enhancement mode or the depletion mode.
In the case of either the NAND type mask ROM, or the NOR type mask ROM, a word line is driven into a select state, and readout of data is executed according to magnitude of an electric current flowing between the bit line and the source line. That is, a select memory cell is disposed between the bit line and the source line, and the readout of the data is executed according to the magnitude of the electric current flowing between the bit line and the source line at the time when the word line corresponding thereto is selected. The bit lines are normally precharged to a predetermined voltage level, and readout of the data is executed according to magnitude of a change in bit line voltage, from a pre-charge voltage, at the time of selection of the memory cell. There have been proposed various configurations for the mask ROM in order to execute quick and stable readout of data.
With the NOR type mask ROM, use is normally made of a configuration of 1-cell/bit wherein 1-bit data is stored in one memory cell to meet demands for high-density while use is generally made of a configuration of 2-cells/bit wherein 1-bit data is stored in two memory cells to meet demands for high-speed.
Patent Document 1 (Japanese Unexamined Patent Publication No. Hei 9 (1997)-8255) has disclosed a configuration of a NAND type ROM wherein a distance between a source line and a ground line in a memory cell is kept constant regardless of a position of a select memory cell, inside a memory cell array, thereby attempting to achieve improvement on noise margin at the time of reading data. In Patent Document 1, as for a bit line in a select column, utilized as a source line for memory cells in an adjacent column, a memory cell current is caused to flow to a bit line in the adjacent column by a pre-charge current. Bit lines at symmetrical positions in the memory cell array are connected to dummy cells disposed outside the memory cell array, respectively, to thereby generate a reference current, and the memory cell current, and the reference current are subjected to differential amplification by a sense amplifier. With Patent Document 1, an attempt is made to keep source line resistance of the respective memory cells constant regardless of positions of the select columns, inside the memory cell array, by utilizing the bit line adjacent to a select bit line as the source line.
In Patent Document 2 (Japanese Unexamined Patent Publication No. 2001-203331), there is shown a ROM of a hierarchical bit line configuration, wherein a dummy cell is disposed at opposite ends of main bit lines in pairs, respectively, thereby differentially reading current changes of the main bit lines in pairs, respectively. With the adoption of the hierarchical bit line configuration, implementation of quick readout is attempted by reducing the number of memory cells connected to sub-bit lines, respectively, to accordingly reduce parasitic capacitances of the main/sub-bit lines, respectively. The dummy cells are each kept in the non-conducting state at all times, functioning as parasitic capacitance. A memory cell transistor is set to an enhancement mode or a depletion mode according to stored data, and data is read by differentially amplifying respective potentials of the main sub-bit lines, generated due to a current fed from a current supply source, flowing via a select memory cell, and respective potentials of reference main sub-bit lines.
In Patent Document 3 (Japanese Unexamined Patent Publication No. 2001-358235), there has been disclosed a ROM of a hierarchical bit line configuration, as with the case of Patent Document 2, wherein dummy cells connected to main bit lines are each made up of a MOS transistor (an insulated gate field effect transistor) with a source and a drain, mutually connected to each other. By so doing, parasitic capacitance of the dummy cell, for a bit line, is created by source junction capacitance and drain junction capacitance, and is rendered twice as large as parasitic capacitance of the memory cell, thereby reducing the number of the dummy cells in an attempt to attain higher density of the memory cells in a memory cell array.
In Patent Document 4 (Japanese Unexamined Patent Publication No. Hei 11 (1999)-191298), there has been disclosed a ROM of a hierarchical bit line configuration, wherein a sub-bit line is provided with a transistor for discharging in order to speed up readout of data, and the conducting state/non conducting state of the transistor for discharging is controlled by use of an inverting signal of a control signal for a block select gate transistor disposed between the sub-bit line, and a main bit line. With Patent Document 4, a read-cycle time is shortened by discharging the sub-bit lines at a higher speed, thereby attempting to speed up the readout of data. At the time of reading data, potentials of select main/sub-bit lines are differentially amplified with the use of unselect main/sub-bit lines serving as reference bit lines.
In Patent Document 5 (Japanese Unexamined Patent Publication No. Hei 7 (1995)-211086), there has been disclosed an array division structure for dividing a memory cell array into two arrays, wherein a word line driver is disposed between the arrays, a memory cell is selected in the array selected, and a memory cell current is detected by a sense amplifier while in the array unselected, a bit line is coupled to a sense amplifier corresponding thereto, and by the agency of an output signal thereof, timing for reading data is determined. A word line is in unselect state in the array unselected, and a bit line load remains constant regardless of stored data of the memory cell, so that a bit line charge speed becomes constant, which is utilized in this case.    [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 9 (1997)-8255    [Patent Document 2] Japanese Unexamined Patent Publication No. 2001-203331    [Patent Document 3] Japanese Unexamined Patent Publication No. 2001-358235    [Patent Document 4] Japanese Unexamined Patent Publication No. Hei 11 (1999)-191298    [Patent Document 5] Japanese Unexamined Patent Publication No. Hei 7 (1995)-211086